(1) Field of the Invention
The present invention relates to a signal transmission circuit, so-called shift register, in particular, to the shift register for driving Liquid Crystal Display (LCD) and Metal Oxide Semiconductor (MOS) image sensor.
(2) Description of the Related Art
FIG. 1 is a circuit diagram showing a structure example of a conventional signal transmission circuit, and describes the four stages of the circuit comprising multiple stages (refer to Japanese Patent publication No. H3-75960 (FIG. 3)). This signal transmission circuit comprises the output transistor to the next stage T12, T22, T32 and T42, the bootstrap capacitor C1, C2, C3 and C4, the bootstrap capacitor charging transistor T11, T21, T31 and T41, the first discharging transistor T13, T23, T33 and T43 and the second discharging transistor T14, T24, T34 and T44.
Each element of this signal transmission circuit is provided with, at least, one or more than one of the source voltage VDD, the driving pulses V1 and V2 and the start pulse VST.
The operations performed by the conventional signal transmission circuit of such structure as described above will be explained as following. When the start pulse VST rises to the logical “High” level, the bootstrap capacitor charging transistor T11 of the first stage turns on. Thus, the electric charge is charged in the bootstrap capacitor C1 until the electric voltage becomes (the source voltage VDD—the threshold voltage Vt1 of the transistor T 11).
When the charging voltage of the bootstrap capacitor C1 exceeds the threshold voltage of the output transistor T12, the output transistor T12 of the first stage turns on. Then, after the driving pulse V1 of the logical “High” level is inputted into the drain of the output transistor T12, the voltage of the driving pulse V1 and the potential difference between the both ends of the bootstrap capacitor C1 are added and applied to the gate of the output transistor T12. When the gate potential (the node N11) of the output transistor T12 rises higher than the potential of the driving pulse V1, the driving pulse V1 gets outputted as the output pulse OUT1 from the node N12.
At the same time, when (i) the voltage of the node N12 is applied to the gate of the bootstrap capacitor charging transistor T21 of the second stage, (ii) the transistor T21 turns on, and (iii) the bootstrap capacitor C2 is charged to the source voltage VDD while the charging voltage does not fall for the threshold voltage Vt2 of the transistor T21.
When the charging voltage of the bootstrap capacitor C2 exceeds the threshold voltage of the output transistor T22, the output transistor T22 of the second stage turns on. Then, after the driving pulse V2 of the logical “High” level is inputted into the drain of the output transistor T22, the potential of the driving pulse V2 and the potential difference between the both ends of the bootstrap capacitor C2 are added and applied to the gate of the output transistor. When the gate voltage (the node N21) of the transistor T22 rises higher than the potential of the driving pulse V2, the driving pulse V2 is outputted as the output pulse OUT2 from the node N22.
At the same time, when the voltage of the node N22 is applied to the gate of the bootstrap capacitor charging transistor T31 of the third stage, the transistor T31 turns on. Thus, the bootstrap capacitor C3 is charged to the source voltage VDD without falling for the threshold voltage Vt3 of the transistor T32.
When the charging voltage of the bootstrap capacitor C3 exceeds the threshold voltage of the output transistor T32, the output transistor T32 of the third stage turns on.
Such operations as described above are repeated, and the signal transmission circuit further sequentially outputs the output pulse Out3 and Out4.
FIG. 2 is a circuit diagram showing a structure example of a conventional error operation preventative signal transmission circuit. In this improved signal transmission circuit, the source voltage is certainly applied to the gate of the bootstrap capacitor charging transistor, while in the conventional signal transmission circuit shown in FIG. 1, only the lower voltage than the source voltage VDD was applied to the gate of the bootstrap capacitor charging transistor. This error operation preventative signal transmission circuit prevents (i) the voltages of the nodes N11, N21, N31 and N41 from gradually falling and (ii) the output pulses from stopping at several stages forward.
The error operation preventative signal transmission circuit shown in FIG. 2 is different from the signal transmission circuit shown in FIG. 1, and it further comprises the first error operation preventative transistor T35 and T45, respectively for the circuit of the third and the fourth stages. As for the transistor T35, (i) the gate is connected to the source (the node N12) of the output transistor T12, (ii) the drain is connected to the source (the node N31) of the bootstrap capacitor charging transistor T31, and (iii) the source is earthed. As for the transistor T45, (i) the gate is connected to the source (the node N22) of the output transistor T22, (ii) the drain is connected to the source (the node N41) of the bootstrap capacitor charging transistor T41, and (iii) the source is earthed.
In addition, the error operation preventative signal transmission circuit shown in FIG. 2 is different from the signal transmission circuit shown in FIG. 1 in that the gate of the second discharging transistor of each stage is connected to the source of the output transistor of the next stage. For example, the gate of the second discharging transistor T14 of the first stage is connected to the source of the output transistor T22 of the second stage.
The operations performed by the error operation preventative signal transmission circuit will be explained as following.
FIG. 3 is a time chart showing the pulse voltage of each unit in the conventional signal transmission circuit using only NMOS. This circuit is a 3V type circuit, wherein the voltage amplitude of the driving; pulses V1 and V2 and the source voltage VDD are 3V.
However, the voltage amplitude of the start pulse VST is 5V. Here, the reason why only the source voltage of the start pulse VST is 5V is because only in the bootstrap capacitor charging transistor T11 of the first stage where the start pulse VST is inputted, the high voltage from the previous stage cannot be provided. Therefore, only the start pulse VST drives the transistor T11 with the voltage amplitude of 5V which is higher than 3V of the driving pulses V1 and V2; prevents the voltage from falling in the transistor T11; and enables the bootstrap capacitor C1 to charge up to 3V of the source voltage VDD.
In FIG. 3 at the time T0, when the start pulse VST rises to 5V, the bootstrap capacitor charging transistor T11 of the first stage turns on; and the bootstrap capacitor C1 is charged toward the source voltage VDD. Here, even if the bootstrap capacitor charging transistor T11 is an enhancement type NMOS, without the influence of the threshold voltage Vt1 of the transistor T11, the voltage VN11 of the node N11 where the gate of the output transistor T12 is connected is charged up to 3V of the source voltage VDD; and the output transistor T12 turns on.
At the time T1, when the driving pulse V1 of 3V is inputted into the drain of the output transistor T12, the voltage HB1 is applied to the gate (the node N11) of the output transistor T12, said voltage HB1 being the combination of the driving pulse V1 of 3V and the potential difference between the both ends of the bootstrap capacitor C1 (3V−Vt1); and the pulse of the amplitude H1 is outputted from the node N12.
At the same time, the voltage HB1 of the node N11 is applied to the gate of the bootstrap capacitor charging transistor T21 of the second stage; the transistor T21 turns on; and the bootstrap capacitor C2 is charged to the source voltage VDD without falling for the threshold voltage of the transistor T21. When the charging voltage of the bootstrap capacitor C2 (the node N21) exceeds the threshold voltage of the output transistor T22, the output transistor T22 of the second stage turns on.
Simultaneously, the voltage of the node N21 is applied to the gate of, the bootstrap capacitor charging transistor T31 of the third stage. Thus, the transistor T31 turns on, and the bootstrap capacitor C3 is charged to the voltage(3V−Vt3) lowered for the threshold voltage Vt3 of the transistor T31. In this state, in the case the driving pulse V1 is 3V which is a logical “High” level, when the driving pulse V1 is outputted to the output node N12 of the first stage, the pulse of the amplitude less than the driving pulse of V1 is also outputted to the output node N32 of the third stage. To solve this problem, the plus terminal of the bootstrap capacitor C3 is set close to the earth voltage; and in order for the output transistor T32 of the third stage to turn off, the error operation preventative transistor T35 is connected between the plus terminal of the bootstrap capacitor C3 and the earth voltage. In other words, the drain of the error operation preventative transistor T35 is connected to the plus terminal of the bootstrap capacitor C3; the source of T35 is connected to the earth voltage; and the gate is connected to the output node N12 of the first stage. Also, when the driving pulse V1 is appearing in the output node N12 of the first stage, the error operation preventative transistor T35 is turned on; the potential of the node N31 is set close to the earth voltage; thereby the driving pulse V1 is prevented from appearing in the output node N32 of the third stage.
In the same manner, the plus terminal of the bootstrap capacitor C4 is connected to the drain of the error operation preventative transistor T45; the earth voltage is connected to the source of the T45; the gate of T45 is connected to the output node N22 of the two stages forward; thus, the error operation is prevented through all the stages.
However, in the processes of a low-voltage driving and a fast operation, it is necessary to set the threshold voltage low for the output transistor such as the output transistor T32. In the error operation preventative method wherein only the plus terminal of the bootstrap capacitor C3 is set close to the earth voltage, the output transistor such as the output transistor T32 turns on; and the voltage with the amplitude lower than V1 and V2 of the driving pulse is outputted to the node N32 and all the nodes of the backward stages corresponding to the node N32. Therefore, the pulse output occurs in other places than the designated places for the pulse output, and the signal transmission circuit does not operate normally. For example, at the time T1, the error operation preventative transistor T35 has “ON” electrical resistance; the potential of the node N31 does not completely become 0; thus the output transistor T32 turns on.
In the future processes of the low-voltage driving and the fast operation of the circuit, this error operation will appear prominently.